1. Field of the Invention
The present invention relates to a PLC-type delay demodulation circuit including a planar lightwave circuit that is formed on one PLC chip and demodulates a DQPSK modulated optical signal.
2. Description of the Related Art
In a 40 Gbps DQPSK communication system, as a method of configuring a delay circuit that demodulates a DQPSK (Differential Quadrature Phase Shift Keying)-modulated signal (optical signal) in a PLC, a method has been proposed which configures the delay circuit including an optical splitter and two MZIs (for example, see Hashimoto, Toshikazu, et al., “Compact DQPSK Demodulator with Interwoven Double Mach-Zehnder Interferometer using Planar Lightwave Circuit,” ECOC 2008 Proceeding, Mo.3.C.2). In the device, it is necessary to reduce the size of a module, power consumption, and polarization dependence and obtain uniform MZI characteristics.
Bits of the optical signals that have been modulated by the delay circuit and then output from four output ends need to be input to four light receiving elements substantially at the same time. Therefore, the lengths of the optical paths from the optical splitter to the four output ends need to be exactly equal to each other.
In order to meet the requirements and solve the problems, a technique for designing a circuit to reduce the size of a chip has been proposed (for example, see Japanese Patent Application Laid-Open (JP-A) No. 2009-244483). In the technique disclosed in JP-A No. 2009-244483, as shown in FIG. 12, in a DQPSK delay circuit including an optical splitter 3 and two MZIs 4 and 5, the two MZIs are formed so as to overlap each other in the same region, in order to reduce the size of the DQPSK delay circuit.
However, in the technique disclosed in JP-A No. 2009-244483, in order to make the lengths of the optical paths from the optical splitter 3 to the four output ends equal to each other, the MZIs 4 and 5 are designed such that the distances from the optical splitter 3 to input couplers 6 and 10 of the MZIs 4 and 5 are equal to each other, the lengths of short delay lines 9 and 13 of the MZIs are equal to each other, and the distances from output couplers 7 and 11 of the MZIs to the output ends are equal to each other. Therefore, the flexibility of the design is reduced and there are restrictions in reducing the size or setting the positions of the input and output ends. In addition, the delay lines need to intersect each other at four points, that is, the arm waveguides 8 and 9 of the MZI 4 need to intersect the arm waveguides 12 and 13 of the MZI 5 at four points, and it is difficult to increase the intersection angle between the arm waveguides, which results in an increase in loss.
The invention has been made in order to meet the requirements and solve the above-mentioned problems, and proposes the layout of a new PLC-type delay demodulation circuit. An object of the invention is to provide a PLC-type delay demodulation circuit that has a small size and is capable of improving the flexibility of the design and reducing loss.